"Topics to Consider When Analyzing a Flight FPGA Design”
Michael J. McDonnell
Ball Aerospace & Technologies Corporation
This paper will present various topics that should be analyzed before a flight FPGA is programmed. Flight FPGA devices are expensive parts and need to be designed right the first time. Performing a thorough analysis is a must. This paper will talk about the following concepts:
Safe State Machines
A simple state machine will be analyzed using two different synthesis engines and the differences will be discussed.
Are negative edge flip-flops introduced into your design?
Global Reset Circuit Synthesis Pitfall
A common global reset circuit will be discussed.
Are buffers inserted after your clock driver (CLKINT)?
Clock Skew in Routed Clocks
An Actel application note for measuring clock skew will be reviewed.
Can you effectively measure clock skew in your routed clocks and correct it?
Actel's SmartTime Static Timing Analysis (STA) Tool
A brief review of the major functions of Actel's SmartTime STA tool will be discussed.
Is your design meeting all timing constraints?
Reports and Constraint Files from Actel’s Designer Tool
A discussion of the valuable reports and constraint files that Actel’s Designer tool can produce are discussed.
Does your design contain latches, negative-edge clocked flip-flops, clamping diodes, active high CLEARs or PRESETs on your flip-flops that you did not intend to have?
Adding the previous design analysis topics to your design checklist will help to achieve first pass success of your flight FPGA design.
2006 MAPLD International Conference Home Page