“In-Circuit Verification and Validation of FPGA Systems”
Gregory B. Davis
The phenomenal growth in design size and complexity continues to make the process of FPGA design verification a critical bottleneck for today’s FPGA systems. Limited access to internal signals, advanced FPGA packages, and printed circuit board (PCB) electrical noise are all contributing factors in making design debug and verification the most difficult process of the design cycle. You can easily spend more than 50% of your design cycle time debugging and verifying your design.
The proper choice of an in-circuit debug methodology (embedded logic analyzer vs. external logic analyzer) will reduce your debug time while the wrong approach can significantly extend you debug time. This paper will examine how to select the proper methodology based on your design constraints.
We will also examine some new twists to the external logic analyzer approach that can further reduce your debug by allowing you to quickly change your FPGA probe points without the need to recompile your design and by allowing you to monitor multiple internal signals per pin
2006 MAPLD International Conference Home Page