"Comprehensive SEE Characterization of Flash-Based FPGAs"

Sana Rezgui, J.J. Wang, Natalie Charest, and Brian Cronquist
Actel Corporation

Abstract

Reconfigurable Systems on Chip (SoC) integrated on a single Field Programmable Gate Array (FPGA) constitute an effective ASIC replacement for various applications in the military and aerospace markets. However, if the FPGA configuration memory should lose its content as a result of a single event, consequences on the overall system will be unpredictable.  

Flash based-FPGAs are non-volatile and provide remote in-system reprogramming to support future design iterations and field upgrades. This technology has the advantage of being a secure, low-power, single-chip solution. Unlike volatile memory-based FPGAs, it does not require additional non-volatile memory to load the device configuration data at system power-up. This reduces cost and initialization time and improves system reliability. However, the flash memory cell sensitivity to SEE such as data-retention degradation and wear-out warrants investigation. 

This paper targets the first phase of SEE characterization of the 0.13-μm ProASIC3 product family, a high-performance architecture operational up to 350MHz operation. These products have up to 3 million system gates, 504 kbits of true dual-port SRAM, 616 single-ended I/O, and 300 differential I/O pairs. They also include 1 kbit of on-chip, programmable, nonvolatile Flash ROM memory storage as well as up to 6 integrated phase locked loops (PLLs). 

The A3P1000-PQ208 device from the ProASIC3 product family is selected for this study. Novel test methodologies employed for the SEE characterization will be presented in the final paper. The testing will target five programmable architectural features: 

Radiation tests for the selected product will be performed at TAMU. The experimental results will be reported in the final paper along with additional information on upset mitigation solutions unique for the target device.

 

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