NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

2005 MAPLD International Conference

Ronald Reagan Building and International Trade Center
Washington, D.C.

September 6, 2005

 Reconfigurable High-Performance Computing Seminar

Seminar Leaders:


Advances in high-performance computing and in reconfigurable computing, based on field programmable gate arrays (FPGAs), form the basis for a new paradigm, reconfigurable supercomputing. This is achieved through hybrid systems of microprocessors and FPGAs that can leverage the advances in high-performance computing and FPGAs. Such systems support both fine-grain and coarse-grain parallelism, and can dynamically tune their architecture to fit applications. Developments in this respect are in three areas: networks of reconfigurable computers (NORCs), where job management systems can recognize networked reconfigurable resources and exploit them in a grid computing fashion; reconfigurable clusters, where progress has been also made in programming and managing computer clusters, with reconfigurable co-processors; and reconfigurable massively parallel systems, where smaller versions and prototypes have been created. Programming such systems can be quite challenging as programming FPGA devices can involve hardware design. However, there have been significant developments in compiler technologies and programming tools. This tutorial will introduce the field of reconfigurable supercomputing and its advances in systems, programming, applications, and compilers. Reconfigurable system developments at SRC, Cray, SGI, and Starbridge will be highlighted, and case studies including full application developments will be presented.


Seminar Schedule

Tarek El-Ghazawi is a Professor at the Department of Electrical and Computer Engineering of the George Washington University, and the founding director of the GWU High-Performance Computing Laboratory (HPCL).
Tarek El-Ghazawi

Tarek El-Ghazawi is a Professor at the Department of Electrical and Computer Engineering of the George Washington University, and the founding director of the GWU High-Performance Computing Laboratory (HPCL). Prior to GWU has was with George Mason University. Dr. El-Ghazawi has served as a Visiting Scientist at NASA GSFC and NASA ARC, and in many consulting/advising roles for leading organizations. El-Ghazawi has received his Ph.D. degree in 1988 from New Mexico State University in Electrical and Computer Engineering. Dr. El-Ghazawi’s research focuses on high-performance computing, reconfigurable computing, computer architecture, performance evaluations and remote sensing applications. El-Ghazawi’s research has been sponsored by NASA, DoD, DARPA, NSF, IBM, SGI, Microsoft and other computing and reconfigurable computing vendors. Dr. El-Ghazawi is one of the principal co-authors of the high-performance computing language UPC. Dr. El-Ghazawi has published one book, several book chapters and well over a hundred refereed journal and conference proceedings papers. He has served in many editorial roles and in organizing many conferences and symposia. He is a Senior Member of the IEEE, a member of the ACM, and a member of Phi Kappa Phi.

Duncan A. Buell
Duncan A. Buell

Duncan A. Buell received the B. S. and M. A. degrees in mathematics from the University of Arizona and University of Michigan, respectively, and in 1976 his Ph. D. in mathematics from the University of Illinois at Chicago. He was an assistant and then associate professor in the Department of Computer Science at Louisiana State University in Baton Rouge. In 1986 he joined the Supercomputing Research Center (now the Center for Computing Sciences), a division of the Institute for Defense Analyses, doing high performance computing and computational mathematics research for the National Security Agency. He has written two books and more than fifty research papers in number theory, document and information retrieval, parallel algorithms, and computer architecture. While at IDA he was project manager for the Splash 2 reconfigurable computing project, one of the first successful ventures into the use of Field Programmable Gate Arrays (FPGAs) as the programmable "CPU" in what is now known as a reconfigurable a computing machine. He was also one of the co-founders of the FPGAs for Custom Computing Machines (FCCM) conference held yearly since 1993. In 1997 Dr. Buell was a member of team that received a National Meritorious Unit Citation from Director of Central Intelligence George Tenet for the solution of a long-outstanding problem of national significance. He joined the University of South Carolina as Professor and Chair of the Department of Computer Science and Engineering in October 2000, where he continues research in high performance and reconfigurable computing.

Kris Gaj, associate professor in the Department of Electrical and Computer Engineering at George Mason University

Kris Gaj

Kris Gaj is an associate professor in the Department of Electrical and Computer Engineering at George Mason University. He received his M.S. and Ph.D. degrees in Electrical and Computer Engineering from Warsaw University of Technology, Poland, in 1988 and 1992, respectively. His current research interests include reconfigurable computing, cryptography, computer arithmetic, CAD tools, and hardware/software co-design. He currently teaches several graduate courses on cryptography, network security, reconfigurable computing, and fast implementations of computer arithmetic in hardware and software. He has been leading several research projects, including the development of a reconfigurable hardware accelerator for the gigabit rate Secure Internet Protocol, IPSec, and the development of the Network of Reconfigurable Computers based on LSF job management system. Since June 2002, he has been involved in the research project devoted to the development and analysis of libraries, applications, and new features for several emerging general-purpose reconfigurable computers. He has been an associate editor of two technical journals and a member of the program committees of several cryptographic conferences.

Alan D George, Professor of Electrical and Computer Engineering at the University of Florida

Alan D George

Alan D George is a Professor of Electrical and Computer Engineering at the University of Florida (UF), the flagship university of the fourth largest state in the nation. He founded in 1993 and directs the High-performance Computing and Simulation (HCS) Research Laboratory, a multi-university research facility that has been cited by the NSA as a center of research excellence in high-performance computing and networking. Professor George received the B.S. degree in computer science and M.S. degree in electrical and computer engineering from the University of Central Florida, and the Ph.D. degree in computer science from Florida State University. Prior to joining the faculty at UF in 1997, he served jointly on the faculties at both Florida State University and Florida A&M University for ten years, and prior to that period worked in industry for four years as a computer engineer and group leader at Martin Marietta and General Electric. Professor George’s research interests and teaching activities focus on high-performance computing and communications, most particularly on architectures, networks, services, systems, and applications for reconfigurable, parallel, distributed, and fault-tolerant computing. He has coauthored approximately 90 refereed conference and journal papers and one book, served as principal investigator on funded research projects totaling in excess of $4M, and as co-investigator on many others, from a broad range of federal and industrial sponsors. Dr. George founded the graduate program area of computer systems and networks in ECE at UF, and his most recent academic service includes leadership on numerous committees including chair of the university committee on high-performance computing. His recent professional service includes program and general chair duties for several IEEE conferences and workshops, including founding general chair of the IEEE Workshop on High-Speed Local Networks (HSLN), and member of the editorial board of the Cluster Computing journal.

Seminars: 2005 MAPLD International Conference

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