"FPGA Design of an Integrated CAN and EDAC Soft Core for Spacecraft Applications"

Antonio Roldao1, Martin Unwin1 and Tanya Vladimirova2

1Surrey Satellite Technology Ltd.
2Surrey Space Centre


As Surrey Satellite Technology Limited (SSTL) moves beyond Low Earth Orbit (LEO) missions, there is a need to develop more robust and radiation tolerant systems. Such systems must be flexible and fast enough to meet customer requirements while keeping costs down. Such flexibility has become possible through the extraordinary developments in Field Programmable Gate-Arrays (FPGAs) technologies. With families ranging from simple low cost, to full-blown hybrids that include multiple embedded processors, FPGAs provide an ideal alternative solution to Application-Specific Integrated Circuits (ASICs). In shifting from Commercial Off-The-Shelf (COTS) ASICs and moving towards FPGA based systems, SSTL is able to take advantage of an unprecedented freedom. Whereas before, FPGAs were only used to provide glue-logic and simple functionality, such as of a Triple Memory Redundancy (TMR), now these devices have become capable of agglomerating the Central Processing Unit (CPU) as well as various peripherals.

This paper describes recent developments at SSTL, where an existing FPGA design consisting of an interface and an Error Detection And Correction (EDAC) module was extended to integrate a controller area network (CAN) module. Several CAN intellectual property (IP) cores were investigated for this application. The European Space Agency's (ESA) HurriCANe core was selected as it is designed for space use, it is small enough for the targeted FPGA, and the source is available for European space applications.

The design and the experiences with the development of this IP Core will be introduced including the purpose-built wrapper and glue logic. It will be described how, by taking advantage of the soft-core nature, the CAN core was adapted to better mesh with the CAN protocol adapted by SSTL for Spacecraft Usage (CAN-SU). Analysis of the advantages and disadvantages of taking such an approach, compared with either using COTS or by having a fully featured System-on-Chip (SoC) solution will be presented.  The paper will also provide a glimpse at the new developments of a Satellite Generic SoC (SG-SoC) that incorporates all the basic functionality of an On Board Computer (OBC), from which by simply plugging-in additional modules, this SG-SoC can easily become a task specific sub-system, such as a Star Sensor or a GPS receiver.

2005 MAPLD International Conference Home Page