Ronald Reagan Building and International Trade Center
September 8-10, 2004
Seminar: VHDL Synthesis for High-Reliability Systems
"VHDL Synthesis for High-Reliability Systems" will be a full-day, 6 hour seminar held on Tuesday, September 7, 2004. It will start at 9:30 am. Break service and lunch will be provided. A working knowledge of VHDL, logic synthesis, and digital design is assumed.
Seminar Topics Will Include:
- Coding Style Recommendations for Portability (The Do's)
- Coding Styles to Avoid (the Don'ts)
- Registers, variables, latches, after, assignments to CLK
- State machine basics
- Creating Safe State machines
- Additional topics/sections:
- Methodology & Design Organization
- Register block outputs (when possible) to reduce potential for long timing paths across blocks (Most important for ASICs where we often synthesize subblocks and then merge them).
- Don't forget your HDL it is hardware.
- Reset (asynchronous, synchronous, and issues)
- Crossing clock boundaries
- Examining the synthesizer's outputs (netlists, documentation).
- Avoiding unreliable structures such as hazards and high-skew clocking networks
- Reuse of "proven" intellectual property
- Replicated flip-flops, pipeline boundaries, and other miscellaneous ways to get into trouble.
- Introduction and a VHDL Synthesis Issue
- A Designer's Checklist
- Methodologies for Reliable Design Implementation
- Reset Circuit Topologies
- VHDL Design Tips and Low Power Design Techniques
- Synthesis Issues: Demonstrated with a Simple Finite State Machine Using Gray Codes
- VHDL Design Review and Presentation
- When Should You and When Should You Not Use VHDL?
- Case Study of a VHDL Design
For more information please contact:
Richard B. Katz
National Aeronautics and Space Administration
2004 MAPLD International Conference Home Page
Home - NASA Office of Logic Design
Last Revised: February 03, 2010
Digital Engineering Institute
Web Grunt: Richard Katz