Test Date: February, 1997
Test Device: Chip Express QYH580
Prepared By: NASA/GSFC (R. Katz)
The QYH580 is a member of the Chip Express QYH500 family. This family is a 0.8 mm bulk CMOS technology. The QYH500 gate array can be configured to yield up to 60,000 usable "gate array gates". This technology utilizes two types of cells: I/O cells and 2 input NAND gates. The I/O cells may be programmed into a variety of configurations: however, there is no storage available in these cells. The two input NAND gates can be configured to provide buffers, logic functions, or flip-flops. The I/O structure is flexible and the devices may have the pins configured per user specifications. For this evaluation, the QYH580 was configured to be pin compatible with an Actel A1280A in a CPGA176 package for both a proof of concept and compatibility with existing test infrastucture. Chip Express is foundryless; the QYH500 series of devices is fabricated by Yamaha.
The QYH500 series is a channeled gate array architecture. Metal routing segments are "pre-placed" in the channels and all possible connections are made during integrated circuit fabrication. The chip is "programmed" by selectively opening connections leaving the interconnect in a state which implements the design netlist. This is opposite of antifuse-based Field Programmable Gate Array (FPGA) technology where connections are made during programming by making an antifuse into a conductor. Note that only a small fraction of possible connections are needed in a gate array; thus in an FPGA a small number of connections must be programmed and in the QYH500 the majority of connections must be made into open circuits.
The QYH500 series, for the purposes of this evaluation, can be programmed using two different techniques for the identical base arrays. The first technique utilizes a laser to remove the unwanted connections and takes on the order of 1 hour at the factory. Turn around for these Laser Programmable Gate Arrays (LPGA) is on the order of days. A one mask technology can remove metal connections from the base array on two levels of metal using a single masking step. In both cases, unused routing segments are left floating. For quick prototypes (as were our test devices) the LPGA is used and the device is not passivated. The 883-qualified devices are processed using one mask technology and are passivated following processing. The devices are qualified for both VCC = 3.3 and 5.0 volts.
This evaluation is considered preliminary: 1 device was used for heavy ion testing, 1 for total ionizing dose (TID) testing, and several unprogrammed devices were used for a quick, coarse, destructive physical analysis. The sample device utilized approximately 35,000 gate array gates, roughly 4 times that of our A1280A 1.0 um samples. It was observed even with the higher gate counts, the dynamic power of the QYH500 was less than the A1280A; static power was essentially 0 uA (our system, as configured, had a measurement resolution of 10 mA.
The CX2000 series of devices is a 0.6 um epi-layer technology fabricated by Tower Semiconductor. This part, which is not currently 883-qualified, will be evaluated in future tests along with additional QYH580 devices.
TID testing was performed at NASA/GSFC using a Co-60 source. The device was statically biased at VCC = 5.0 VDC with all inputs terminated to ground. The dose rate was 5 krads (Si) / day or 0.058 rads (Si) per second. Functional tests were run at each radiation step of 5 krads (Si) as were three device current parameters: standby (the entire chip static), clock on (measuring the clock distribution network), and dynamic, with all elements toggling at approximately 500 kHz.
No functional failures were detected and a plot of ICC vs. radiation and annealing is given below. Testing proceeded to 20 krads (Si). All annealing was biased at VCC = 5.0VDC and was at room temperature.
Heavy ion Single Events Effects (SEE) testing was performed at Brookhaven National Laboratory. The device was monitored for single event upset (SEU), single event latchup (SEL) and device functionality. Strip charts were made of ICC vs. time. Nominal fluence for each run was 1x107 ions/cm2. All runs were performed with VCC in the standard 5.0 VDC ± 10% range; future testing will evaluate the device at 3.3 VDC ±10%.
No functional failures were observed during testing. Latchup was detected at relatively high LETs and is summarized in the chart below. SEU performance was very good with upsets first detected near LET = 40 MeV/mg/cm2with a very small cross-section; the SEU performance is also summarized in a chart below. The good SEU performance is believed to come from the relatively high capacitance of the "pre-laid" metal routing segments. Note that this performance is similar to that observed for Actel C-Module flip-flops in one of it's two storage states which uses a similar routing segment scheme.
Points at the graphs on the 1x10-10 line indicate that no SEE was detected for that run.
Unprogrammed devices from the QYH500 and CX2000 series were subject to a quick, rough, destructive physical analysis. No obvious defects were noted and the preliminary evaluation showed processing consistent with 883 standards. Fully processed samples are expected for a more thorough analysis in the near future.
The CX2000 series has a very high I/O pin count. Note, in the photograph below, that many of the I/O pads are staggered. This can have implications for package selection and chip on board (COB) or multi-chip modules (MCMs).
Last Revised: February 03, 2010
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