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David L. Hanley, Jayne Partridge and Eldon C. Hall
The procedure for the testing, screening, and lot rejection of integrated circuits for the Apollo Guidance and Navigation computer is described. The procedure, based on a knowledge of failure modes failure mechanisms and contributing causes to failures in the manufacturing of devices, attempts to increase the reliability of integrated circuits. This is accomplished by screening and analyzing weak devices and using the generated data to quantitatively assess the lot for acceptance, rework or rejection. The technique, which is primarily aimed toward high-usage high-volume devices, was developed after extensive testing of many tens of thousands of integrated circuits. The process documents included in the appendix contain stress test procedures, classification of failure modes, numerical rejection limits per class of failure modes, internal visual rejection criteria, and leak test procedures.
To emphasize the need for the described technique data is presented showing variations among vendors and variation among procurement lots shipped from a single vendor. The contributing factors to the variations are discussed.
A discussion of the evolution of the process documents is presented. The ultimate goal of the documents is the elimination or minimization of detected failure modes. Failure studies have shown that some failure modes are screenable with high confidence whereas attempts to screen other types of failure modes merely decrease the life of the device. In the latter case, the detection during short term stressing of devices which exhibit long time dependent failure modes is a low probability event. After one-hundred-percent nondestructive testing, sample destructive testing, failure analysis and failure mode grouping the classes of failure modes in a lot are then weighted in accordance with screenbility and detecetabliity. Failure of a lot within the acceptable limits will instigate action as to whether the lot will be rescreened, resubmitted to tighter acceptable limits, or whether a portion of the lot or the entire lot will be rejected. The decision for lot or sublot rejection is based on the traceability of the nonscreenable failure modes to a critical manufacturing process. The approach presents a continuous monitoring procedure for qualification of parts and vendors, and creates an incentive on the part of the vendor to eliminate causes of failures.
Eldon C Hall
A case history of the integrated circuit used for the logic in the Apollo Guidance Circuit is given. Achieving the required goals of low weight, volume, and power coupled with extreme high reliability necessitated the use of one single, simple integrated circuit for all logic functions. A brief description of the evolution of the computer design is given along with a general discussion of some of the engineering and design problems which arise with the use of a standardized semiconductor monolithic integrated circuit.
The flight qualification procedure is described. After the qualified suppliers list has been formed, each lot shipped from any qualified supplier is exposed to a screen and burn-in procedure followed by failure analysis of generated failures. The lot is accepted or rejected on the basis of the number of failures generated and the types of failure modes generated. The reliability history of the NOR Gate is given showing differences among vendors, showing differences among lots shipped from a single vendor, and updated field failure rates.
The enclosed discussion of computer displays is taken from the minutes of a monthly progress meeting. This presentation is based on a very early iteration of the display problem. Substantial changes are expected to result from the overall display analysis which is underway.
And readers of this page may be interested in:
The decision, in 1962, to design the AGC using integrated circuit logic devices was critical to Apollo Computerís success and a key moment in the history of computing. Eldon Hall's Journey to the Moon recounts this decision process.
Following are copies of integrated circuit purchase orders for components required in the evaluation processes and the view graphs used to report the evaluationís conclusions to the NASA Program Office.
Apollo Documentation Master Page
Home - NASA Office of Logic Design
Last Revised: February 03, 2010
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