INTRODUCTION
Some modern digital systems implement feedback circuits that enable circuits to perform with precision timing. The key design consideration is to make the overall circuit insensitive to variables such as the variability associated with the manufacture of the components, temperature, voltage, radiation, and end of life changes in propagation delay.
However, these positive characteristics of digital closed loop feedback systems may mask either damaged components or indications that components may not be healthy. Monitoring key signals via engineering telemetry enables the test engineer to determine the amount of performance margin in the system, detect "out of family" circuit performance, and to "trend" the performance of the system.
An example circuit from the Lunar Orbiter Laser Altimeter (LOLA) will be given showing the concept. Additionally, the LOLA circuit scheme will be used to demonstrate how testability can readily be designed into circuits such as these.
EXAMPLE SYSTEM
The block diagram shown below (details such as synchronization circuits not shown) in Figure 1 is a part of the LOLA electronics. This closed loop system uses an ultra-stable oscillator for internal calibration with the time-to-digital converter (TDC) producing a pulse-width modulated signal that is normally input into an amplifier. If the TDC's internal gates are determined to be operating too slowly when compared against the reference, then the pulse width of the control output will increase, indicating to the amplifier to increase it's output level. Similarly, if the TDC's internal gates are operating too fast, then the output pulse width decreases with the amplifier responding by decreasing its output level.
For the LOLA application, the pulse-width modulated signal is input into a logic network that works in one of several modes: 1) pass through; 2) forced low; and 3) forced high. The output of the TDC is also fed into a monitoring circuit, shown in the right of the block diagram of Figure 1. In the LOLA system, there are 12 TDCs and associated control and support electronics circuits.
Figure 1. Block diagram of time-to-digital converter (TDC)
closed loop feedback circuit and monitoring circuit.CONTROL CIRCUITS
There are several characteristics of this circuit that will briefly be described.
The "phase_connect_su" register is initialized to all zero's upon the application of power. After the TDCs are configured by other FPGA logic (not shown here) a '1' is shifted into the shift register at a rate of 35.7 ms per shift. This has the effect of avoiding a large step load when the system is turned on.
The "phases_mask" register is initialized to all one's upon the application of power. This register is controlled via ground command and can turn off the amplifiers to each of the TDCs on an individual basis. This is useful for determining the power level of each individual TDC, turning off a malfunctioning circuit in flight, and driving the monitoring circuit to measure the maximum possible duty cycle, 100%. Since the amplifier will see a constant '0' input, the TDC will attempt to compensate by increasing the duty cycle of its output.
The "force phase" register is also controlled via ground command and can be used to set the amplifier to its maximum output. In response, the selected TDC will attempt to compensate by decreasing the duty cycle of it's output, which is driven into the monitoring circuit, which would measure the minimum possible duty cycle, 0%. A 4-to-12 bit decoder is used so that only one amplifier can be driven to it's maximum voltage at a time, eliminating a possible high power state of the system.
MONITORING CIRCUIT
The monitoring circuit is located on the right of Figure 1. Since the nominal frequency of the TDCs output is approximately 40 kHz, a 20 MHz sampling circuit is used along with a 24-bit accumulator and a 10 ms gate time, giving the monitor ample resolution. The LOLA electronics measures the duty cycle of each of the 12 TDCs every 35.7 ms (28 Hz). The accumulator is reset to all zero's at the initiation of each 35.7 ms "minor frame" and then is incremented or decremented based on the value of the TDC control output. Thus, positive values of the accumulator correspond to duty cycles greater than 50% and negative values of the accumulator correspond to duty cycles less than 50%.
TEST EQUIPMENT MONITOR
The LOLA engineering test equipment is programmed to read out TDC phase measurements over the instrument electronic's MIL-STD-1553B command and telemetry interface. A sample display is shown in Figures 2A and 2B below.
The test software can display the data in either raw hexadecimal format or a more user friendly percentage. This allows the test engineer to rapidly determine the state of each of the 12 digital control feedback loops. In the examples below, the engineering model being tested only had 6 of the 12 TDCs populated on the circuit board. The unused inputs were tied off resulting in the 100% duty cycle measurement.
The test equipment, for each TDC, produces three values: real-time data, a minimum, and a maximum. These statistics allow the test equipment to record a history of each TDC's performance, useful for capturing transients during long test runs.
Figure 2A: Sample LOLA engineering monitor.
6 of 12 TDCs are populated in this engineering model system.
Figure 2B: LOLA engineering model showing TDC duty cycles and statistics.
Home - NASA Office of Logic Design
Last Revised:
February 03, 2010
Web Grunt:
Richard Katz
