Please e-mail comments and suggestions for these guidelines and criteria.
A. Supply Sequencing (some devices can be damaged by incorrect sequencing): There are two major cases to be concerned with here. This section will cover multiple supplies for a single device. The next circuit will cover the interface between multiple devices. Many of the newer technology devices require two or more power supplies. Often these are divided into supplies to power the core of a logic device and a second supply to operate the Input/Output cells. Additional supplies may be needed for PLL's and DLL's, special I/O standards, or various bias supplies such as external charge pumps. It is obvious that the supplies must meet all of the DC standards as well as ripple characteristics, particularly for circuits such as PLLs. What is often not obvious is that the sequence that power is supplied to a single device can, in certain cases, affect both circuit behavior and performance as well as reliability. For certain devices, such as SX-S series devices, if the I/O supply is brought up before the logic core, then a large inrush current may be present; this would not be the case if the order of the supplies was reversed. For certain devices, incorrect power sequencing can result in overstress or damage. This is the case for multiple vendors. Often the requirements for sequencing are in either application notes or the "fine print." One case to consider is when the oscilloscope probe "slips" and the ground ring momentarily contacts either a power lead or a capacitor terminal, momentarily shorting a supply. This may result incorrect sequencing and can in principle overstress or damage certain chips. In general, avoid parts with power supply sequencing requirements. When present, they should be flagged and the design should be done very carefully, incorporating circuit protection as required.
B. Signals Into Unpowered CMOS I/O's: Similar to A, above, the power supply sequencing between interfacing IC's, either on the same or separate boards, must be carefully considered. Many IC's, particularly CMOS ones, present a low impedance to the system when powered off. Most of these IC's require that the power supply be brought up prior to the application of signals on either the inputs or the outputs (many FPGA outputs also have inputs active in the general purpose I/O modules). Some programmable IC's are not analyzable by inspection; the particular design configuration must be known. For instance, some I/O modules provide for cold sparing; that is, they present a high impedance to the system when powered off. That same I/O, configured differently, may have clamp diodes switched in while powered off for PCI compatibility. The design details are often needed to do a proper worst-case analysis.
C. Startup Current Transients: Startup current transients are common in many modern devices. The size of the current can be a function of time between power cycles, temperature, ramp rate of the supply, radiation exposure history, power supply sequencing, etc. These currents can be rather large for certain devices, often as high as several amps. It is critical that the power supply systems do not limit current in these cases to steady state levels with margin as insufficient current during the startup sequence can result either a failure to properly initialize, power device shutdown or recycling in an infinite loop, or a system lockup, the deadly embrace. Similarly, some parts have hard restrictions on minimum and maximum power supply rise times; failure to meet these levels may result in circuit failure.
D. Bypassing and Distribution: Modern logic devices can be rather large, consisting of multiple millions of gates. Synchronous design techniques, high operating frequencies, and large I/O counts can result in a challenge to the power distribution and conditioning system. Most of the manufacturers supply details in application notes. While some of their recommendations may seem like overkill with a large number of bypass capacitors, at times consisting of multiple capacitors of different values, it is understood that these notes are not written to make their parts harder to design with. These rules should be followed unless suitable care is given to the analysis and test of the system for worst-case conditions. Reconfigurable logic can be exploited to generate worst-case patterns to ensure high-fidelity power and then replaced with the flight application. JTAG interfaces may also be used and care should be given that the JTAG test patterns do not violate design limits, such as SSOs. Common errors often include simply not following the manufacturers' recommendations with, for example, not having bypass capacitors on all sides of a quad flat pack.
E. On-card Regulators and Voltage Margin Testing: As described above, it is common for modern digital devices to have multiple supplies. Indeed, as noted in Old News #18: New FPGA Technologies: Currents, Voltages, and Temperatures, the tolerance on these supplies may be quite tight, particularly for the voltage supplied to the logic device's core. It is a common practice to use an on-card low voltage dropout regulator low voltage dropout regulator to generate and supply the core voltage from a higher voltage supplied to the card. This higher voltage may be used for "noisy" applications such as I/O voltage supply, and/or other functions.
However, it is also a frequent occurrence that designers of digital electronics cards while including a voltage regulator on the board, simply connect the output of the regulator to its loads. This presents testability issues as their design does not permit voltage margin testing of the digital system. Such testing is required to serve as a check against static timing analysis and back-annotated simulation runs, good testing of the logic devices over the range of voltages expected over the course of the mission, and to aid in the detection of faulty components. The requirement for voltage margin testing is not new, and goes back at least to 1971! See Section 4.4 Testing and Checkout.of NASA SP-8070 which includes the following:
The ease of checkout during acceptance and qualification tests and, particularly, during prelaunch activities should be considered during the design of the computer.
Provision should be made for varying all primary and secondary voltages for onboard margin testing.
Voltage margin testing of these systems can be facilitated by not connecting the output of the voltage regulator directly to the loads, but instead routing the output to the connector that brings power in, going through a small loop in the harness, and then bringing the voltage line back onto the card. It is strongly recommended that the wire 'loop' be redundant. Thus, when the loop is installed for operations, the digital logic components operate from the on-card regulator, and a Hall Effect current meter can be used. For testing operations, the power harness is connected to a commercial power supply, enabling the control and monitoring of all primary and secondary voltages. This is used for onboard margin testing and for tests involving power sequencing. Such an arrangement facilitates testing during thermal testing, permitting thermal-voltage margin testing which gives a good signature of the board's and design's health, while not requiring that the mechanical box be opened and not requiring that any jumpers be soldered and unsoldered to gain access to any onboard supplies.
Designers Must Take Care When Powering High-Speed CMOSXL, Robert M. Hanrahan, ED Online ID #5415, Electronic Design, August 4, 2003.
"RT54SX32S High ICCI Inrush Current," OLD News #10, May 16, 2003.
"Analysis of Printed Circuit Board Artwork: Bypassing," Rod Barto, Office of Logic Design, March 2004.
"PCB Layout Issues," presented at "Design Seminar on Actel SX-A and RTSX-S Programmed Antifuses," Tuesday, April 13, 2004, NASA Goddard Space Flight Center. Discusses layout issues for bypass capacitors, vias, and power and ground planes, in the context of "before and after" of a flight printed circuit board.
Old News #18: New FPGA Technologies: Currents, Voltages, and Temperatures
"Spaceborne Digital Computer Systems," NASA SP-8070, March 1971. See Section 4.4 Testing and Checkout.
Low Voltage Dropout Regulators and DC-DC Converters.
TOP LEVEL: "Design Guidelines and Criteria for Space Flight Digital Electronics"
Last Revised: February 03, 2010
Web Grunt: Richard Katz