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Mongoose V SEE Test Results

 

SYNOPSIS V1.0:
HEAVY ION-INDUCED SINGLE EVENT EFFECT MEASUREMENTS ON THE
MONGOOSE V MICROPROCESSOR

Robert A. Reed1, Kenneth Li1, Dwaine Molock2 and Donald Hawkins1

1. NASA/Goddard Space Flight Center, Greenbelt, Maryland 20771
2. Daedalian System Corporation, Greenbelt, Maryland 20771

TEST DATE: November 8, 1997.
REPORT DATE: November 18, 1997

I. INTRODUCTION

This study was undertaken to determine the single event effect response of the Synova/Honeywell Mongoose V microprocessor. The microprocessor was interrogated for single event effects (SEE) by exposing them to heavy ion irradiations at Brookhaven National Laboratory’s Single Event Upset Test Facility. The microprocessor performed several different functions during irradiations.

II. DEVICES TESTED

DUT

Device

Manufacturer

LDC Serial number

DUT Bias

1

MV-P-02

Synova/Honeywell

9727

1038

4.2 V

2

MV-P-02

Synova/Honeywell

9727

1039

4.2 V

3

MV-P-02

Synova/Honeywell

9727

1042

4.5 V


III TEST FACILITY

Facility: Brookhaven National Laboratory’s Single Event Upset Test Facility.
Flux: 1.1x104 to 1.7x105 particles/cm2/s.
Maximum fluence: 5.0x107 particles/cm2.
Ions used during exposures: (all LETs reported in this synopsis are not corrected for overlayer)

Ion Species

LET normal to the die surface (MeV-cm2/mg)

Range (mm)

Br

37

39

I

60

34

Au

82

28

IV. TEST METHODS

Temperature: 25o C
Software: A diagnostic software suite developed at NASA/GSFC to test several functions and processes of the Mongoose V is used to interrogate the DUT for errors.
Functions or processes tested: The possible sources of error during each test are the CPU, UART, BIU, DRAM controller, and the blocks of the microprocessor used to perform the function or process. See the summary of results table for a complete description.

V. SUMMARY OF SEU TEST RESULTS

 

Mode

Function or Process Initialization and Test Procedure

Single Event Upset Results

1

CPU, UART, BIU and DRAM CONTROLLER – EDAC DISABLED 1.User defines process.
2.Start process.*
3.End process.
4.Goto 2 until user interrupt.**
Single event upsets were not observed. Maximum LET was 83 MeV-cm2/mg. The error cross section is less than 1x10-7 cm2/device.

2

CPU, UART, BIU and DRAM CONTROLLER – EDAC ENABLED 1.User defines process.
2.Start process.*
3.End process.
4.Goto 2 until user interrupt.**
Single event upsets were not observed. Maximum LET was 83 MeV-cm2/mg. The error cross section is less than 1x10-7 cm2/device.

3

I-CACHE (data and tag RAMS)

D-CACHE (data and tag RAMS)

 

Two independent test for each Cache.

1.User defines pattern.
2.Write*
3.Read and check
4.Slave report to host error count.
5.Goto 2 until user interrupt**.
Cache single event upsets occurred in two of the three devices. The exposure levels for all runs were greater than or equal to 1x107 particles/cm2. At most two upsets occurred during any exposure.

DUT 1 (bias=4.2V): Single event upsets were not observed. Maximum LET was 83 MeV-cm2/mg. The error cross section is less than 1x10-7 cm2/device.

DUT 2 (bias=4.2V): Single event upsets were observed. A portion of the data:

Effective LET        SEU Cross Section
(MeV-cm2/mg)          (cm2/device)
        96                1x10-7 1x10-7
        43                4x10-8 4x10-8
        37                < 2x10-8 (no SEUs were
                             observed at this LET)

DUT 3 (bias=4.5V): Single event upsets were observed. A portion of the data:

Effective LET        SEU Cross Section
(MeV-cm2/mg)          (cm2/device)
        96                 1x10-7 1x10-7
        69                 2.2x10-8 2.2x10-8
        60                 < 2.5x10-8 (no SEUs were
                             observed at this LET)

4

FPU 1.User defines function
2.Begin calculation*
3. Slave reports P/F
4. Goto 2 until user interrupt.
Single event upsets were not observed. Maximum LET was 96 MeV-cm2/mg. The error cross section is less than 4x10-8 cm2/device.

5

INTERNAL 32-bit TIMER #1 and #2 1.User defines count down seed.
2.run test*
3. Slave reports interrupt.**
Single event upsets were not observed. Maximum LET was 96 MeV-cm2/mg. The error cross section is less than 4x10-8 cm2/device.

6

DYNAMIC AUTOMATIC WAITSTATE GENERATOR-External memory test and read from known I/O location 1.Write data to location

2.Read data and compare.*

3. Slave reports P/F

4. Goto 2 until interrupt.**

 

Single event upsets were not observed. Maximum LET was 83 MeV-cm2/mg. The error cross section is less than 1x10-7 cm2/device.

*Begin irradiation after completion of this step.
**Stop irradiation.

VI. SUMMARY

The Synova/Honeywell Mongoose V processor preformed very well under stringent single event upset testing. Only fourteen cache single event upsets occurred during the entire exposure of the three Mongoose processors to several different ion species. One anomaly occurred during an irradiation where the LET was 83 MeV-cm2/mg. The source of this anomaly is unknown. The maximum LET at the surface of the die was 96 MeV-cm2/mg. The integral particle fluence for all exposures that have LETs at the die surface of 37 MeV-cm2/mg or greater was 6.7x108 particles/cm2. All measured single event upset cross sections at all LETs were less than 1x10-7 cm2/device.

VII ACKNOWLEDGMENTS

We wish to acknowledge the efforts of Dennis Andrucyk and Ken LaBel at NASA/GSFC, Bert Schmidt from Synova, Gary Hubbard and Patrick Schmidt at Honeywell SSEC (Plymouth, Mn), and Gary Gardner Honeywell (Clearwater, Fl). Without their efforts, this test would not have been possible.


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