Stefan Rusu, Gadi Singer
IEEE Journal of Solid-state Circuits
The first implementation of the IA-64 architecture achieves high performance by using a highly parallel execution core, while maintaining binary compatibility with the IA-32 instruction set. Explicitly parallel instruction computing (EPIC) design maximizes performance through hardware and software synergy. The processor contains 25.4 million transistors and operates at 800 MHz. The chip is fabricated in a 0.18-um CMOS process with six metal layers and packaged in a 1012-pad organic land grid array using C4 (flip-chip) assembly technology. A core speed back-side bus connects the processor to a 4-MB L3 cache.
Notes - Interesting use of parity and EDAC along with skew control.
Tam, S.; Rusu, S.; Nagarji Desai, U.; Kim, R.; Ji Zhang; Young, I.
IEEE Journal of Solid-State Circuits
The clock design for the first implementation of the IA-64 microprocessor is presented. A clock distribution with an active distributed deskewing technique is used to achieve a low skew of 28 ps. This technique is capable of compensating skews caused by within-die process variations that are becoming a significant factor of the clock design. The global, regional and local clock distributions are described. A multilevel skew budget and local clock timing methodology are used to enable a high-performance design by providing support for intentional clock skew injection and time borrowing. By providing a test access port interface to the deskew architecture and the incorporation of the on-die-clock-shrink, this design is equipped with two very powerful post-silicon timing debug tools that are critical to high-performance microprocessor design and enabled quick time-to-market.
Last Revised: January 09, 2002
Digital Engineering Institute
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