Stefan Rusu, Gadi Singer
IEEE Journal of Solid-state Circuits
The first implementation of the IA-64 architecture achieves high performance by using a highly parallel execution core, while maintaining binary compatibility with the IA-32 instruction set. Explicitly parallel instruction computing (EPIC) design maximizes performance through hardware and software synergy. The processor contains 25.4 million transistors and operates at 800 MHz. The chip is fabricated in a 0.18-um CMOS process with six metal layers and packaged in a 1012-pad organic land grid array using C4 (flip-chip) assembly technology. A core speed back-side bus connects the processor to a 4-MB L3 cache.
Notes - Interesting use of parity and EDAC along with skew control.
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