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A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.


29CPL154

Title and Reference Abstract


Reconfigurable, System-on-Chip, High-Speed Data Processing and Data Handling Electronics

1999 MAPLD International Conference
September 28-30, 1999
Laurel, Maryland

Presentation:
D2_Kleyner_S.pdf
D2_Kleyner_S.ppt

Paper:
D2_Kleyner_P.pdf
D2_Kleyner_P.doc

Abstract
This paper presents a methodology and a tool set which implements automated generation of moderate-size blocks of customized intellectual property (IP), thus effectively reusing prior work and minimizing the labor intensive, error-prone parts of the design process. Customization of components allows for optimization for smaller area and lower power consumption, which is an important factor given the limitations of resources available in radiation-hardened devices. The effects of variations in HDL coding style on the efficiency of synthesized code for various commercial synthesis tools are also discussed.

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